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5,0 mm x 6,4 mm www .ti.com d2 r1 r2 d1 and r o u t 1 r o u t 2 d i n 2 d i n 1 enen d o u t 1 + d o u t 1 ? d o u t 2 ? d o u t 2 + r i n 2 ? r i n 2 + r i n 1 ? r i n 1 + 12 3 4 5 6 7 8 1615 14 13 12 1 1 10 9 r i n 1 - r i n 1 + r i n 2 + r i n 2 - d o u t 2 - d o u t 2 + d o u t 1 + d o u t 1 - enr o u t 1 r o u t 2 gndv c c d i n 2 d i n 1 en sn65lvds049 slls575 ? august 2003 dual lvds differential drivers and receivers the intended application of this device and signaling features technique is for point-to-point baseband data trans- ds90lv049 compatible mission over controlled impedance media of approxi- up to 400 mbps signaling rates mately 100- w characteristic impedance. the trans- mission media may be printed-circuit board traces, flow-through pin-out backplanes, or cables. (note: the ultimate rate and 50 ps driver channel-to-channel skew (typ) distance of data transfer is dependent upon the attenu- 50 ps receiver channel-to-channel skew ation characteristics of the media, the noise coupling to the environment, and other application specific charac- (typ) teristics) 3.3-v power supply the sn65lvds049 is characterized for operation from high-impedance disable for all outputs ? 40 c to 85 c internal failsafe biasing of receiver inputs 1.4 ns driver propagation delay (typ) 1.9 ns receiver propagation delay (typ) functional diagram high impedance bus pins on power down ansi tia/eia-644-a compliant receiver input and driver output esd ex- ceeds 10 kv 16-pin tssop package applications full-duplex lvds communications of clock and data printers descriptionthe sn65lvds049 is a dual flow-through differential line driver-receiver pair that uses low-voltage differen- tial signaling (lvds) to achieve signaling rates as high as 400 mbps. the tia/eia-644-a standard compliant electrical interface provides a minimum differential out- pw package (marked as lvds049) (top view) put voltage magnitude of 250 mv into a 100- w load and receipt of signals with up to 1 v of ground potential difference between a transmitter and receiver. the lvds receivers have internal failsafe biasing that places the outputs into a known high state for uncon- nected differential inputs. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. production data information is current as of publication date. copyright ? 2003, texas instruments incorporated products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily in- clude testing of all parameters.
www .ti.com sn65lvds049 slls575 ? august 2003 driver truth table input enables outputs (1) din en en d out+ d out- l h l or open l h h h l x all other conditions z z (1) h = high level, l = low level, x = irrelevant, z = high impedance (off) receiver truth table differential input enables output (1) r in- - r in+ en en r out v id 3 100 mv h l or open h v id - 100 mv l open/short or terminated h x all other conditions z (1) h = high level, l = low level, x = irrelevant, z = high impedance (off) enable function table enables outputs en en lvds out lvcmos out l or open l or open disabled disabled h l or open enabled enabled l or open h disabled disabled h h disabled disabled power dissipation rating circuit board t a 25 c derating factor (1) t a = 85 c package model power rating above t a = 25 c power rating pw low-k (2) 774 mw 6.2 mw/ c 402 mw (1) this is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. (2) in accordance with the low-k thermal metric definitions of eia/jesd51-3. 2
www .ti.com 2 . 4 v i d 2 v i d 2 sn65lvds049 slls575 ? august 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) unit supply voltage range (2) , v cc -0.3 v to 4 v d in , r out , en, or en -0.3 v to (v cc + 0.3 v) voltage range r in+ or r in- -0.3 v to 4 v d out+ or d out- -0.3 v to 3.9 v r in+ , r in- , d out+ , and d out- 10 kv human body model (3) esd all pins 2k v charged-device model (4) all pins 500 v lvds output short circuit duration (dout+, dout-) continuous continuous power dissipation see dissipation rating table storage temperature range -65 c to 150 c lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 c (1) stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability (2) all voltage values, except differential i/o bus voltages, are with respect to network ground terminal. (3) tested in accordance with jedec standard 22, test method a114-a. (4) tested in accordance with jedec standard 22, test method c101. recommended operating conditions min nom max unit supply voltage, v cc 3 3.3 3.6 v receiver input voltage gnd v common-mode input voltage, v ic v v cc - 0.8 v operating free-air temperature, t a -40 85 c 3
www .ti.com sn65lvds049 slls575 ? august 2003 device electrical characteristics over recommended operating conditions (unless otherwise noted) parameter test conditions min typ (1) max unit input dc specifications (d in , en, en ) v ih input high voltage 2.0 v cc v v il input low voltage gnd 0.8 v i ih input high current v in = v cc -10 3 10 a i il input low current v in = gnd -10 1 10 a v cl input clamp voltage i cl = -18 ma -1.5 -0.8 v lvds output dc specifications (d out+ , d out- ) |v od | differential output voltage 250 350 450 v change in magnitude of v od for d |v od | -35 1 35 mv complimentary output states r l = 100 w , see figure 1 v os offset voltage 1.125 1.2 1.375 v change in magnitude of v os for d v os -25 1 25 mv complimentary output states enabled i os output short circuit current d in = v cc and d out+ = 0 v, or -4.5 -9 ma d in = gnd and d out- = 0 v i osd differential output short circuit current (2) enabled, v od = 0 v -3.6 -9 ma i off power-off leakage v cc = 0 v or open; -20 0 20 a vo = 0 or 3.6 v i oz output high-impedance current en = 0 v and en = v cc , -10 0 10 a v o = 0 or v cc lvds input dc specifications (r in+ , r in- ) v it+ differential input high threshold 100 mv v cm = 1.2 v, 0.05 v, 2.35 v v it- differential input low threshold -100 mv v cmr common-mode voltage range v id = 100 mv 0.05 2.35 v v cc = 3.6 v, v in = 0 v or 2.8 v -20 20 a i in input current v cc = 0 v, v in = 0 v, 2.8 v, or 3.6 v -20 20 a outputs dc specifications (r out ) v oh output high voltage i oh = -0.4 ma, v id = 200 mv 2.7 3.3 v v ol output low voltage i ol = 2 ma, v id = -200 mv 0.05 0.25 v i oz output high-impedance current disabled, v out = 0 v or v cc -10 0 10 a device dc specifications i cc power supply current en = 3.3 v, d in = v cc or gnd, 100 - w 17 35 ma (lvds loaded, enabled) differential lvds loads i ccz high impedance supply current (disabled) no loads, en = 0 v 1 25 ma (1) all typical values are at 25 c and with a 3.3 v supply. (2) output short circuit current (ios) is specified as magnitude only, the minus sign indicates direction only 4
www .ti.com sn65lvds049 slls575 ? august 2003 switching characteristics over operating free-air temperature range (unless otherwise noted) parameter test conditions min typ (1) max unit lvds outputs (d out+ , d out- ) t plhd differential propagation delay low to high r l = 100 w , 1.3 2.0 ns c l = 15 pf distributed, t phld differential propagation delay high to low 1.4 2.0 ns see figure 2 t sk(p) differential pulse skew (|t phl - t plh |) 0 0.15 0.4 ns t sk(o) differential channel-to-channel skew (2) 0 0.05 0.5 ns t sk(pp) differential part-to-part skew (3) 0 1 ns t r differential rise time 0.2 0.5 1 ns t f differential fall time 0.2 0.5 1 ns t phz disable time, high level to high impedance r l = 100 w , 2.7 4 ns c l = 15 pf distributed, t plz disable time, low level to high impedance 2.7 4 ns see figure 3 t pzh enable time, high impedance to high level 1 5 8 ns t pzl enable time, high impedance to low level 1 5 8 ns f max maximum operating frequency (4) 250 mhz lvcmos outputs (r out ) t plh propagation delay low to high v id = 200 mv, 0.5 1.9 3.5 ns c l = 15 pf distributed, t phl propagation delay high to low 0.5 1.7 3.5 ns see figure 4 t sk(p) pulse skew (|t phl - t plh |) 0 0.2 0.4 ns t sk(o) channel-to-channel skew (5) 0 0.05 0.5 ns t sk(pp) part-to-part skew (6) 0 1 ns t r rise time 0.3 0.5 1.4 ns t f fall time 0.3 0.5 1.4 ns t phz disable time, high level to high impedance c l = 15 pf distributed, 3 7.2 9 ns see figure 5 t plz disable time, low level to high impedance 2.5 4 8 ns t pzh enable time, high impedance to high level 2.5 4.2 7 ns t pzl enable time, high impedance to low level 2 3.3 7 ns f max maximum operating frequency (7) 200 250 mhz (1) all typical values are at 25 c and with a 3.3 v supply. (2) t sk(o) is the magnitude of the time difference between the t plh or t phl of all drivers of a single device with all of their inputs connected together. (3) t sk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. (4) f (max) generator input conditions: t r = t f < 1 ns (0% to 100%), 50% duty cycle, 0 v to 3 v. output criteria: duty cycle = 45% to 55%, v od > 250 mv, all channels switching. (5) t sk(lim) is the maximum delay time difference between drivers over temperature, v cc , and process. (6) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate wf(max) generaith the same supply voltages, at the same temperature, and have identical packages and test circuits (7) f (max) generator input conditions: t r = t f < 1 ns (0% to 100%), 50% duty cycle, v id = 200 mv, v cm = 1.2 v. output criteria: duty cycle = 45% to 55%, v oh > 2.7 v, v ol < 0.25 v, all channels switching. 5
www .ti.com v c c 7 v 7 v 300 k w 300 k w r i n r i n v c c 7 v 50 w 300 k w en,en ,d i n v c c 50 w d o u t 7 v 10 k w v c c 50 w 7 v r o u t r l /2 v c c gnd d i n driver enabled d o u t + d o u t - v o s v o d r l /2 sn65lvds049 slls575 ? august 2003 equivalent input and output schematic diagrams parameter measurement information figure 1. driver v od and v os test circuit 6
www .ti.com pulse generator 1.5 v 80 % 20 % 80 % 20 % t 0 v* 0 v 0 v 1.5 v 0 v* *differential * * * oscilloscope 50 w d o u t + c1c2 d o u t - d i n 50 w 50 w * matched 50 cables, c = 15 pf distributed blocking capacitors c1 = c2 = 50 nf t p l h d t p l l d 3 v0 v v o h v o l v o d = d o u t + - d o u t - t r t f d i n d o u t - d o u t + v o d * matched 50 w cables, c = 15 pf distributed pulse generator 2.4 v oscilloscope 50 w 50 w 50 w ** 950 w 950 w 1 k w 1 k w * v c c gnd d o u t - d i n en or en d o u t + 100 w 1.5 v 50 % 1.5 v v oh v ol 0 v 3 v 1.5 v 1.5 v 0 v 3 v 50 % 50 % 50 % 1.2 v 1.2 v t p h z t p z h t p l z t p z l en when en = gnd or open d o u t + when d i n = gnd d o u t - when d i n = v c c en when en = v c c d o u t - when d i n = gnd d o u t + when d i n = v c c sn65lvds049 slls575 ? august 2003 figure 2. driver propagation delay and rise/fall time test circuit and waveforms figure 3. driver high-impedance state delay test circuit and waveforms 7
www .ti.com 1.5 v 80 % 20 % 80 % 20 % 1.5 v 1.2 v 1.3 v1.1 v vid = 200 mv pulse generator * * * * * 50 w 50 w 50 w 950 w r o u t * matched 50 w cables, c = 15 pf distributed r i n + r i n - 100 w oscilloscope t p l h t p h l t r t f 0 v differential v o h v o l r i n - r i n + r o u t * * 50 % v oh v ol 0 v 3 v 50 % v cc /2 0.5 v v cc /2 1.5 v 1.5 v 0 v 3 v 1.5 v 1.5 v pulse generator 1.4 v 1 v oscilloscope * matched 50 w cables, c = 15 pf distributed 100 w 50 w 50 w 950 w v c c 1 k w r i n + r i n - r o u t en or en t p h z t p h z 0.5 v t p l z t p z l en when en = gnd or open en when en = v c c r o u t for r i n + = 1.4 v and r i n - = 1 v r o u t for r i n + = 1 v and r i n - = 1.4 v sn65lvds049 slls575 ? august 2003 figure 4. receiver propagation delay and rise/fall test circuit and waveforms figure 5. receiver high-impedance state delay test circuit and waveforms (note, v cc = 3.3 v) 8
www .ti.com 0 100 200 300 400 500 600 40 60 80 100 120 140 160 v c c = 3.3 v , t a = 25 c |v od - differential output v oltage - mv | r l - load resistance - w 0 10 20 30 40 50 60 0.1 1 10 100 1000 i cc - supply current - ma f - frequency - mhz single receiver single driver v c c = 3.3 v , t a = 25 c, r l = 100 w , c l = 15 pf distributed, v i d = 400 mv p - p, v i = 3 v all switching sn65lvds049 slls575 ? august 2003 typical characteristics power supply current v od vs. load resistance vs. frequency figure 6. figure 7. 9
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) SN65LVDS049PW active tssop pw 16 90 green (rohs & no sb/br) cu nipdau level-1-260c-unlim SN65LVDS049PWg4 active tssop pw 16 90 green (rohs & no sb/br) cu nipdau level-1-260c-unlim SN65LVDS049PWr active tssop pw 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim SN65LVDS049PWrg4 active tssop pw 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs) or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 4-nov-2005 addendum-page 1
mechanical data mtss001c january 1995 revised february 1999 post office box 655303 ? dallas, texas 75265 pw (r-pdso-g**) plastic small-outline package 14 pins shown 0,65 m 0,10 0,10 0,25 0,50 0,75 0,15 nom gage plane 28 9,80 9,60 24 7,90 7,70 20 16 6,60 6,40 4040064/f 01/97 0,30 6,60 6,20 8 0,19 4,30 4,50 7 0,15 14 a 1 1,20 max 14 5,10 4,90 8 3,10 2,90 a max a min dim pins ** 0,05 4,90 5,10 seating plane 0 8 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0,15. d. falls within jedec mo-153
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